HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 579

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
8
7
6
5
4
3
2
1
0
IFC2
IFC1
IFC0
BFC2
BFC1
BFC0
PFC2
PFC1
PFC0
Bit Name
Initial Value
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CPU Clock Frequency Division Ratio Setting
These bits specify the CPU clock frequency
division ratio with respect to the input clock or
PLL circuit 1 output frequency.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/6
101: ×1/8
Other than above: Setting prohibited
Bus Clock Frequency Division Ratio Setting
These bits specify the bus clock frequency
division ratio with respect to the input clock or
PLL circuit 1 output frequency.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/6
101: ×1/8
Other than above: Setting prohibited
Peripheral Clock Frequency Division Ratio
Setting
These bits specify the peripheral clock frequency
division ratio with respect to the input clock or
PLL circuit 1 output frequency.
000: ×1/2
001: ×1/3
010: ×1/4
011: ×1/6
100: ×1/8
Other than above: Setting prohibited
Rev. 2.00 Feb. 12, 2010 Page 495 of 1330
REJ09B0554-0200