HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 660

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 17.2 Register Configuration (2)
Rev. 2.00 Feb. 12, 2010 Page 576 of 1330
REJ09B0554-0200
1
Ch. Register Name
0
Serial error register 0
Serial mode register 1
Bit rate register 1
Serial control register 1
Transmit FIFO data register 1
Serial status register 1
Receive FIFO data register 1
FIFO control register 1
Transmit FIFO data count
register 1
Receive FIFO data count
register 1
Serial port register 1
Line status register 1
Serial error register 1
Serial mode register 0
Bit rate register 0
Serial control register 0
Transmit FIFO data register 0
Serial status register 0
Receive FIFO data register 0
FIFO control register 0
Transmit FIFO data count
register 0
Receive FIFO data count
register 0
Serial port register 0
Line status register 0
SCRER0
SCSMR1
SCBRR1
SCSCR1
SCFTDR1 Undefined Undefined
SCFSR1
SCFRDR1 Undefined Undefined
SCFCR1
SCTFDR1 H'0000
SCRFDR1 H'0000
SCSPTR1 H'0000*
SCLSR1
SCRER1
Abbrev.
SCSMR0
SCBRR0
SCSCR0
SCFTDR0 Undefined Undefined
SCFSR0
SCFRDR0 Undefined Undefined
SCFCR0
SCTFDR0 H'0000
SCRFDR0 H'0000
SCSPTR0 H'0000*
SCLSR0
H'0000
H'0000
H'FF
H'0000
H'0060
H'0000
H'0000
H'0000
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
H'0000
H'FF
H'0000
H'0060
H'0000
H'0000
2
3
H'0000
H'0000
H'FF
H'0000
H'0060
H'0000
H'0000
H'0000
H'0000*
H'0000
H'0000
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
H'0000
H'FF
H'0000
H'0060
H'0000
H'0000
H'0000
H'0000*
H'0000
3
2
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by
Hardware
*
5
Standby
by
Software/
Each
Module
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained