HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 241

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
10, 9
8
7
6
5
4
3
2
Bit Name
⎯
ICE
OIX
⎯
ORA
⎯
OCI
CB
Initial Value
All 0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Enable Bit
Selects whether the IC is used. Note however
when address translation is performed, the IC
cannot be used unless the C bit in the page
management information is also 1.
0: IC not used
1: IC used
OC Index Enable Bit
0: Effective address bits [13:5] used for OC entry
1: Effective address bits [25] and [12:5] used for
When the ORA bit is 1, this bit should be cleared
to 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
OCRAM Bit
When the OC is enabled (OCE = 1), this bit
specifies whether half of the OC is to be used as
RAM. When the OC is disabled (OCE = 0), this
bit should be cleared to 0.
0: Normal mode (the entire OC is used as a
1: RAM mode (half of the OC is used as a cache
When the OIX bit is 1, this bit should be cleared
to 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
OC Invalidation Bit
When 1 is written to this bit, the V and U bits of
all OC entries are cleared to 0. This bit is always
read as 0.
Copy-Back Bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
selection
OC entry selection
cache)
and the other half is used as RAM)
Rev. 2.00 Feb. 12, 2010 Page 157 of 1330
REJ09B0554-0200