HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 269

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
8.2
Table 8.1 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 8.1
Exception
Category
Reset
General
exception
Exception Types and Priorities
Execution
Mode
Abort type
Re-
execution
type
Completion
type
Exception Sources and Priorities
Exception
Power-on reset
Manual reset
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception 1
User break before instruction
execution*
Instruction address error
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
Slot illegal instruction exception 2
General FPU disable exception 2
Slot FPU disable exception
Data address error (read)
Data address error (write)
Data TLB miss exception (read) 2
Data TLB miss exception (write) 2
Data TLB protection
violation exception (read)
Data TLB protection
violation exception (write)
FPU exception
Initial page write exception
Unconditional trap (TRAPA)
User break after instruction
execution*
1
1
Priority
Level
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Priority
Order
1
2
1
3
4
0
1
2
3
4
4
4
4
5
5
6
6
7
7
8
9
4
10
Rev. 2.00 Feb. 12, 2010 Page 185 of 1330
Vector
Address
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
(VBR/DBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR/DBR)
Offset
H'100/— H'1E0
H'100
H'400
H'100
H'100
H'100
H'100
H'100
H'100
H'100
H'400
H'400
H'100
H'100
H'100
H'100
H'100
H'100/— H'1E0
REJ09B0554-0200
Exception
Code
H'060
H'160
H'000
H'020
H'000
H'140
H'140
H'0E0
H'040
H'0A0
H'180
H'1A0
H'800
H'820
H'0E0
H'100
H'040
H'0A0
H'0C0
H'120
H'080

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