HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 784

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
19.6.2
In order to set up the master interface to receive a data packet on the I
steps.
(1) Load the clock control register:
(a) Set SCL clock generation divider (SCGD) to 01h.
(b) Set clock division factor (CDF) is set to 2h.
(2) Load the master control register and address:
(a) Set address of slave being accessed to master address register and the STM1 bit (read mode:
(b) Set the Master Control Register to 89h.
(3) Wait for the address to be output:
(a) Wait for master events (interrupts by the MAT bit and MDR bit in the master status register).
(b) Set the master control register to 88h (the master device keeps the SCL low level until the
(c) Reset the MAT bit to 0.
(4) Monitor the progress of data byte reception:
(a) Wait for a master event (the MDR bit in the master status register).
(b) Read data from receive data register.
(c) Set the master control register to 8Ah.
(d) Reset the MDR bit.
(5) Wait for the end of transmission:
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REJ09B0554-0200
(SCL frequency of 400 kHz)
(Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz)
1).
(MDBS = 1, MIE = 1, and ESG = 1)
MDR bit is cleared in order to suspend the data reception).
If only one data byte is to be transmitted, set the master control register 8Ah. (This enables the
stop generation). This generates a stop on the bus as soon as one byte has been received.
If the byte preceding the last byte transmitted by the slave device is to be received, for the last
one-byte receive interrupt, i.e., MDR interrupt,
(Set the force stop control bit).
(a) Execute processing of the last byte receive interrupt (MDR), i.e., extract the data and clear
MDR.
Master Receiver (Single Buffer Mode)
2
C Bus Interface
2
C bus, take the following