HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 662

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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17.3.1
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting
with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to SCFRDR, automatically.
SCRSR cannot be directly read from and written to by the CPU.
17.3.2
SCFRDR is an 8-bit FIFO register of 128 stages that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until SCFRDR is full (128 data
bytes).
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in SCFRDR, an undefined value will be
returned. When SCFRDR is full of receive data, subsequent serial data is lost.
Rev. 2.00 Feb. 12, 2010 Page 578 of 1330
REJ09B0554-0200
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
R
7
7
-
-
-
R
6
6
-
-
-
R
5
5
-
-
-
R
4
4
-
-
-
R
3
3
-
-
-
R
2
2
-
-
-
R
1
1
-
-
-
R
0
0
-
-
-

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