HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 227

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.6
To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read
from and written to by a P2 area program with a MOV instruction in privileged mode. Operation
is not guaranteed if access is made from a program in another area. A branch to an area other than
the P2 area should be made at least eight instructions after this MOV instruction. The ITLB and
UTLB are allocated to the P4 area in the physical address space. VPN, V, and ASID in the ITLB
can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as
data array 2.
VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D,
WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both
the address array side and the data array side. Only longword access is possible. Instruction
fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be
specified; their read value is undefined.
6.6.1
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the
entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address
field bits [1:0].
In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID.
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
2. ITLB address array write
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
Memory-Mapped TLB Configuration
ITLB Address Array
Rev. 2.00 Feb. 12, 2010 Page 143 of 1330
REJ09B0554-0200