HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 758

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
Rev. 2.00 Feb. 12, 2010 Page 674 of 1330
REJ09B0554-0200
Bit
2
1
0
Bit Name
TSBE
FSB
ESG
2
C Bus Interface
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Start Byte Transmission Enable
Setting TSBE to 1 will have the master transmit a
start byte (01H) onto the bus after each start or
restart is issued. The start byte is used for
interfacing with a microcomputer with a lower
operating frequency which supports to the I
interface.
Force Stop onto the Bus
Setting FSB to 1 will have the master issue a stop
onto the bus at the end of the current transfer. If
ESG is also 1, the master immediately issues a
start and begins transmitting a new data packet. If
ESG is 0, the master enters the idle state.
Set FSB to 1 when the TEND flag is set to 1
during transmission in the FIFO buffer mode, or
when the RDF flag is set to 1 during reception in
the FIFO buffer mode.
In single buffer mode, when the last bit of a byte
is transmitted/received, the I
FSB value and enters the STOP state. Therefore,
to stop the transfer after a specified number of
bytes are transferred, the FSB bit must be set to 1
before the last byte is transferred.
Note: Check section 19.7, Usage Notes, when
Enable Start Generation
Setting ESG to 1 will have the master start
transmission of a data packet. If the bus is idle
when ESG is set to 1, the master issues a start
onto the bus and then issues the slave address. If
the master is transferring data when ESG is set to
1, the master issues a restart before transmitting
the slave address at the end of that data byte
transfer. In the case of data packet transmission,
ESG must be reset by software after the slave
address is transmitted; if not reset, a restart is
issued after each time the transmission is
completed.
using this bit.
2
C module latches the
2
C bus