HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 590

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 506 of 1330
REJ09B0554-0200
Bit
5
4
3
2
1
0
Bit Name
RSTS
WOVF
IOVF
CKS2
CKS1
CKS0
Initial Value
0
0
0
0
0
0
R/W Description
R/W Reset Select
R/W Watchdog Timer Overflow Flag
R/W Interval Timer Overflow Flag
R/W
R/W
R/W
Specifies the kind of reset to be performed when
WTCNT overflows in watchdog timer mode. This
setting is ignored in interval timer mode.
0: Power-on reset
1: Manual reset
Indicates that WTCNT has overflowed in watchdog
timer mode. This flag is not set in interval timer
mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
Indicates that WTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
Clock Select 2 to 0
These bits select the clock used for the WTCNT
count from eight clocks obtained by dividing the
input clock of Frequency divider 1×1 clock. When
PLL1 is switched on or off, the clock after the
switching is used. The overflow cycles shown below
are for use of a 33-MHz input clock and PLL circuit
1 on (×6).
000:
001:
010:
011:
100:
101:
110:
111:
Up counting may not be performed correctly if bits
CKS2 to CKS0 are modified while the WDT is
running. Always stop the WDT before modifying
these bits.
Clock Division Ratio
1/32
1/64
1/128
1/256
1/512
1/1024
1/2048
1/4096
Overflow Cycle
41 μs
82 μs
164 μs
328 μs
656 μs
1.31 ms
2.62 ms
5.25 ms