HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1025

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.3.2
CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction
with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits
TY4 to TY2 specify the additional settings. All of bits TY4 to TY2 should be cleared to 0 or only
one of them should be set to 1. Bits TY4 to TY2 can only be set to 1 if the corresponding settings
in TY1 and TY0 allow that setting.
Bit
7 to 5
4
3
2
1
0
Command Type Register (CMDTYR)
Bit
Name
⎯
TY4
TY3
TY2
TY1
TY0
Initial value:
Initial
Value
All 0
0
0
0
0
0
R/W:
Bit:
7
-
0
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Type 4
Set this bit to 1 when specifying the CMD12 command.
Bits TY1 and TY0 should be set to 00.
Type 3
Set this bit to 1 when specifying stream transfer. Bits
TY1 and TY0 should be set to 01 or 10.
The command sequence of the stream transfer
specified by this bit ends when it is aborted by the
CMD12 command.
Type 2
Set this bit to 1 when specifying multiblock transfer.
Bits TY1 and TY0 should be set to 01 or 10.
The command sequence of the multiblock transfer
specified by this bit ends when it is aborted by the
CMD12 command.
Types 1 and 0
These bits specify the existence and direction of
transfer data.
00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Setting prohibited
R
5
0
-
TY4
R/W
4
0
R/W
TY3
3
0
Rev. 2.00 Feb. 12, 2010 Page 941 of 1330
TY2
R/W
2
0
R/W
TY1
1
0
R/W
TY0
0
0
REJ09B0554-0200