HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 63

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.8 Example of 16-Bit Data Width SRAM Connection ...............................................313
Figure 10.9 Example of 8-Bit Data Width SRAM Connection .................................................313
Figure 10.10 SRAM Interface Wait Timing (Software Wait Only) ............................................314
Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal)..................315
Figure 10.12 SRAM Interface Wait State Timing
Figure 10.13 DCK, BS2, and CS1 Timing when Reading SRAM Interface
Figure 10.14 DCK, BS2, and CS1 Timing when Writing to SRAM Interface
Figure 10.15 Connection Example of Synchronous DRAM with 32-Bit Data Width
Figure 10.16 Basic Timing for Synchronous DRAM Burst Read ...............................................322
Figure 10.17 Basic Timing for Synchronous DRAM Single Read..............................................324
Figure 10.18 Basic Timing for Synchronous DRAM Burst Write ..............................................325
Figure 10.19 Basic Timing for Synchronous DRAM Single Write.............................................327
Figure 10.20 Burst Read Timing .................................................................................................329
Figure 10.21 Burst Read Timing (RAS Down, Same Row Address) ..........................................330
Figure 10.22 Burst Read Timing (RAS Down, Different Row Addresses) .................................331
Figure 10.23 Burst Write Timing ................................................................................................332
Figure 10.24 Burst Write Timing (Same Row Address) .............................................................333
Figure 10.25 Burst Write Timing (Different Row Addresses) ....................................................334
Figure 10.26 Burst Read Cycle for Different Bank and Row Address From Preceding Burst
Figure 10.27 Auto-Refresh Operation .........................................................................................337
Figure 10.28 Synchronous DRAM Auto-Refresh Timing...........................................................337
Figure 10.29 Synchronous DRAM Self-Refresh Timing ............................................................338
Figure 10.30 (1) Synchronous DRAM Mode Write Timing (PALL) ........................................341
Figure 10.30 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ..............342
Figure 10.31 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) ......343
Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM.........................................344
Figure 10.33 Burst ROM Basic Access Timing ..........................................................................346
Figure 10.34 Burst ROM Wait Access Timing ...........................................................................347
Figure 10.35 Burst ROM Wait Access Timing ...........................................................................348
Figure 10.36 Example of PCMCIA Interface ..............................................................................352
Figure 10.37 Basic Timing for PCMCIA Memory Card Interface..............................................353
Figure 10.38 Wait Timing for PCMCIA Memory Card Interface ...............................................354
Figure 10.39 PCMCIA Space Allocation ....................................................................................355
Figure 10.40 Basic Timing for PCMCIA I/O Card Interface ......................................................356
Figure 10.41 Wait Timing for PCMCIA I/O Card Interface .......................................................357
(Read Strobe Negate Timing Setting; AnS = 1, AnW = 011, AnH = 10) .............316
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles) .......................................................317
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles) .......................................................318
(Area 3) ..................................................................................................................320
Read Cycle .............................................................................................................335
Rev. 2.00 Feb. 12, 2010 Page lxi of lxxxii
REJ09B0554-0200