HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1094

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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27.3.7
The MFIADR is a 32-bit register which indicates the address in the MFRAM to be accessed by the
external device via the MFI.
Specifying continuous access to the MFRAM in the LOCK bit in MFIMCR automatically
performs auto-increment (+4) or auto-decrement (-4) of the address according to the AI/AD bit in
MFIMCR, and updates MFIADR each time the external device accesses the MFRAM.
Initial value:
Initial value:
Note:
Rev. 2.00 Feb. 12, 2010 Page 1010 of 1330
REJ09B0554-0200
Bit
31 to 11
10 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
* The external device can write to these bits via the MFI. The on-chip CPU cannot write to
MFI Address Register (MFIADR)
these bits.
31
15
R
R
0
0
-
-
Bit
Name
A10
to
A2
30
14
-
R
-
R
0
0
29
13
R
R
Initial
Value
All 0
All 0
All 0
0
0
-
-
28
12
R
R
0
0
-
-
R/W
R
R/W*
R
27
11
R
0
R
0
-
-
R/W*
A10
26
10
R
0
-
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Address
Specifies the memory space in the 2-Kbyte MFRAM to
be accessed by the external device via the MFI, with 32-
bit alignment.
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W* R/W* R/W* R/W* R/W*
25
A9
R
-
0
9
0
24
A8
R
0
8
0
-
23
A7
R
0
7
0
-
22
A6
R
0
0
6
-
21
A5
R
0
0
5
-
R/W* R/W* R/W*
20
A4
R
0
4
0
-
19
A3
R
0
3
0
-
A2
18
R
0
2
0
-
17
R
0
1
-
0
R
-
16
R
0
0
R
-
0
-

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