HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 841

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Initial value:
Initial value:
Bits
31
30
29 to 7
6
5
4
R/W:
R/W:
Bit:
Bit:
MIE
Bit Name
OC
RHSC
FNO
UE
MIE
R/W
31
15
R
0
0
-
R/W
OC
30
14
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
0
0
All 0
0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R/W
R/W
R
R/W
R/W
R/W
26
10
R
R
0
0
-
-
25
R
R
-
-
0
9
0
Description
Master Interrupt Enable
Setting this bit to 1 will enable an interrupt generation
by the event specified in another bit in this register.
HCD uses this bit to enable the master interrupt. To
use HCD for interrupt detection, use the USB bit of
the INTC.
0: Operation is not affected
1: Interrupt generation is enabled
Ownership Change
0: Operation is not affected
1: Interrupt generation to change HC control is
Reserved
These bits are always read as 0. Always write 0 to
this bit.
Root Hub Status Change
0: Operation is not affected
1: Interrupt generation due to Root Hub Status
Frame Number Overflow
0: Operation is not affected
1: Interrupt generation due to Frame Number
Unrecoverable Error
0: Operation is not affected
1: Interrupt generation due to unrecoverable error is
enabled
Change is enabled
Overflow is enabled
enabled
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
RHSC FNO
Rev. 2.00 Feb. 12, 2010 Page 757 of 1330
R/W
22
R
0
6
0
-
R/W
21
R
0
5
0
-
R/W
UE
20
R
0
4
0
-
R/W
RD
19
R
0
3
0
-
REJ09B0554-0200
R/W
SF
18
R
0
2
0
-
WDH
R/W
17
R
0
1
0
-
R/W
SO
16
R
0
0
0
-

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