HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 20

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
19.6.5 Master
Receiver (FIFO Buffer
Mode)
19.7.1 Restriction 1
19.7.2 Restriction 2
20.3 Register
Descriptions
Table 20.2 Register
Configuration (1)
20.3.1 Control
Register (SSICR)
Rev. 2.00 Feb. 12, 2010 Page xviii of lxxxii
REJ09B0554-0200
Page
703
703, 704 Description replaced
704, 705 Description replaced
709
711
713
Revision (See Manual for Details)
3. Set the RDF trigger value to ICFCR.
4. ICMCR=H'0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0.
5. Wait for MAT, and clear ESG.
6. Wait for RDF, and read the data received from ICRXD.
7. Wait for RDF, and set FSB to 1.
8. Wait for one bit period after setting RDF to 1 and read the
Table amended
Table amended
Ch.
0
1
Bit
11
Bit
15
14
(At this point, the slave address is output onto I
ICFSR=H'0000 0000 (clear the flag)
(Repeat)
data received from ICRXD.
Verify that RDF is 0. (If RDF is 1, read the data from ICRXD
and then clear RDF to 0.)
Register Name
Transmit data register 0
Transmit data register 1
Bit Name
SPDP
Bit Name
SCKD
SWSD
Initial Value
0
Initial Value
0
0
Abbrev.
SSITDR0
SSITDR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Serial Padding Polarity
This bit is ignored if CPEN = 1.
0: Padding bits are low
1: Padding bits are high
Note: When MUEN = 1, the padding bits will be
Description
Serial Bit Clock Direction
0: Serial clock input, slave mode
1: Serial clock output, master mode
Note: In uncompressed mode (CPEN = 0),
Serial WS Direction
0: Serial word select input, slave mode
1: Serial word select output, master mode
Note: In uncompressed mode (CPEN = 0),
P4 Address
H'FE68 0008
H'FE69 0008
at the low level. (The muting function
takes priority.)
(SCKD, SWSD) may only be set to (0, 0)
or (1, 1).
(SCKD, SWSD) may only be set to (0, 0)
or (1, 1).
Area 7 Address
H'1E68 0008
H'1E69 0008
2
C bus.)
Size
32
32
Sync
Clock
Pck
Pck