HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1217

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.3.2
In this section, “1 (2, 3 …) instruction(s) after…”, as a measure of the distance between two
instructions, is defined as follows. A branch is counted as an interval of two instructions.
(1) Example of sequence of instructions with no branch:
100
102
104
106
(2) Example of sequence of instructions with a branch (however, the example of a sequence
L200
31.3.3
The sequence of operations from setting of break conditions to user break exception handling is
described below.
1. Specify pre- or post-execution break in the case of an instruction access, inclusion or exclusion
2. Set the break bus conditions in BBRA and BBRB. If even one of the BBRA/BBRB instruction
of the data bus value in the break conditions in the case of an operand access, and use of
independent or sequential channel A and B break conditions in BRCR. Set the break addresses
in BARA and BARB, set the ASIDs corresponding to the break space in BASRA and BASRB,
and set the address and ASID masking methods in BAMRA and BAMRB. If the data bus
value is to be included in the break conditions, also set the break data in BDRB and the data
mask in BDMRB.
access/operand access select (the ID bit) and read/write select groups (the RW bit) is set to
B'00, a user break interrupt will not be generated on the corresponding channel. Make the
BBRA and BBRB settings after all other break-related register settings have been completed.
If breaks are enabled with BBRA/BBRB while the break address, data, mask register, or the
break control register is in the initial state after a reset, a break may be generated inadvertently.
of instructions with no branch should be applied when the branch destination of a
delayed branch instruction is the instruction itself + 4):
Instruction A (0 instructions after instruction A)
Instruction B (1 instruction after instruction A)
Instruction C (2 instructions after instruction A)
Instruction D (3 instructions after instruction A)
100 Instruction A: BT/S L200 (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B)
200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B)
202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B)
User Break Operation Sequence
Explanation of Terms Instruction Intervals
Rev. 2.00 Feb. 12, 2010 Page 1133 of 1330
REJ09B0554-0200