HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 311

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 9.4
Notes: 1. As shown in table 9.4, eight peripheral modules are assigned to each register. Setting a
9.3.3
ICR sets the input signal detection mode for external interrupt input pin NMI and indicates the
input signal level at the NMI pin.
Initial value:
Register
INTPRI00
INTPRI04
INTPRI08
INTPRI0C
Bit
15
R/W:
Bit:
2. Reserved: These bits are always read as 0. The write value should always be 0.
3. To enable an IRQ4 or IRQ5 interrupt in software standby mode, setting must be made
Interrupt Control Register (ICR)
Bit Name
NMIL
NMIL
31 to 28
IRQ4*
USB
Reserved*
HCAN2(0)
0/1*
value from H'F (1111) to H'0 (0000) in each of the 4-bit groups configures interrupt
priority level for each group. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
in this register as well as in IPRC. The same value must be set in both registers. Note
that software standby mode cannot be exited by an IRQ6 or IRQ7 interrupt.
15
R
Interrupt Request Sources and INTPRI00 to INTPRI0C*
3
MAI
R/W
14
0
2
13
0
-
-
LCDC
27 to 24
IRQ5*
HCAN2(1)
Reserved*
Initial Value
0/1*
12
3
0
-
-
2
11
0
-
-
23 to 20
IRQ6
SSI(0)
DMABRG
MMCIF
10
0
-
-
R/W
R
NMIB NMIE IRLM
R/W
9
0
19 to 16
IRQ7
SSI(1)
SCIF(0)
Reserved*
Description
NMI Input Level
Sets the level of the signal input at the NMI pin.
This bit can be read to determine the NMI pin
level. It cannot be modified.
0: NMI pin input level is low
1: NMI pin input level is high
R/W
8
0
Bits
2
R/W
0
7
15 to 12
Reserved*
HAC(0)
SCIF(1)
MFI
Rev. 2.00 Feb. 12, 2010 Page 227 of 1330
6
0
-
-
2
5
0
11 to 8
Reserved*
HAC(1)
SCIF(2)
Reserved*
-
-
4
0
-
-
1
2
2
7 to 4
Reserved*
I
SIM
ADC
3
0
2
-
-
C(0)
REJ09B0554-0200
2
0
-
-
2
Reserved*
I
HSPI
CMT
3 to 0
2
1
0
-
C(1)
-
0
-
0
-
2