HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 133

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Power-Down State: In a power-down state, CPU halts operation and power consumption is
reduced. The power-down state is entered by executing a SLEEP instruction. There are three
modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details on
power-down states, see section 14, Power-Down Modes.
Bus-Released State: In this state, the CPU has released the bus to a device that requested it.
Transitions between the states are shown in figure 2.5.
Interrupt
Note : In the middle of a bus cycle, it does not change in the manual reset state.
From any state when
RESET = 0
*
Bus request
Bus-released state
Figure 2.5 Processing State Transitions
Bus request
clearance
Power-on reset state
Bus request
Sleep mode
SLEEP instruction
with STBY bit
cleared
Bus
request
RESET = 1
Bus request
Bus request
clearance
clearance
From any state when
RESET = 1 and MRESET = 0
Exception-handling state
Program execution state
Exception
interrupt
RESET = 0
*
End of exception
transition
processing
Rev. 2.00 Feb. 12, 2010 Page 49 of 1330
RESET = 1,
MRESET = 1
SLEEP instruction
with STBY bit set
Manual reset state
Standby mode
Power-down mode
Reset state
REJ09B0554-0200
Interrupt