HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 999

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
31 to 20 ⎯
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1, 0
Bit Name
RW
CA6/SA6
CA5/SA5
CA4/SA4
CA3/SA3
CA2/SA2
CA1/SA1
CA0/SA0
SLREQ3
SLREQ4
SLREQ5
SLREQ6
SLREQ7
SLREQ8
SLREQ9
SLREQ10
SLREQ11
SLREQ12
⎯
Initial Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
Description
Reserved
Always 0 for read and write.
Codec Read/Write Command
0: Notifies the off-chip codec device of a write
1: Notifies the off-chip codec device of a read
Codec Control Register Addresses 6 to 0/
Codec Status Register Addresses 6 to 0
[Write]
Specify the address of the codec register to be
written.
[Read]
Indicate the status address received via slot 1,
corresponding to the codec register whose data
has been returned in HACCSDR.
Slot Requests 3 to 12
Valid only in the Rx frame. Indicate whether the
codec is requesting slot data in the next Tx frame.
Automatically set by hardware, and correspond to
bits 11 to 2 of slot 1 in the Rx frame.
0: Slot data is requested.
1: Slot data is not requested.
Reserved
Always 0 for read and write.
access to the register specified in the address
field (CA6/SA6 to CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair
in the same Tx frame.
When HACACR.TX12_ATOMIC is 0,
transmission of HACCSAR and HACCSDR in
the same Tx frame is not guaranteed.
access to the register specified in the address
field (CA6/SA6 to CA0/SA0).
Rev. 2.00 Feb. 12, 2010 Page 915 of 1330
REJ09B0554-0200