HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 21

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
20.3.1 Control
Register (SSICR)
20.3.2 Status Register
(SSISR)
20.3.3 Transmit Data
Register (SSITDR)
Page
714
715
720
721
Revision (See Manual for Details)
Table amended
Bit
2
Table amended
Figure amended
Initial value:
Initial value:
Bit
8
Bit
0
R/W:
R/W:
Bit:
Bit:
Bit Name
CPEN
Bit Name
DEL
Bit Name
IDST
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial Value
0
Initial Value
0
Initial Value
1
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
26
10
0
0
Rev. 2.00 Feb. 12, 2010 Page xix of lxxxii
R/W
R/W
25
0
0
9
Description
Compressed Mode Enable
0: Compressed mode disabled
1: Compressed mode enabled
Note: In compressed mode (CPEN = 1), only
Serial Data Delay
0: 1 clock cycle delay between SSI_WS and
1: No delay between SSI_WS and SSI_SDATA
Description
Description
Idle Mode Status Flag
Indicates that the serial bus activity has ceased.
This bit is cleared if EN = 1 and the Serial Bus is
currently active.
This bit can be set to 1 automatically under the
following conditions.
SSI = Serial bus master transmitter (SWSD = 1
and TRMD = 1):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed. It can also be
set to 1 when the EN bit has been cleared and the
data that has been written to SSITDR is output on
the serial data input/output pin (SSI_SDATA), j.e.,
the serial data of the system word length is output.
SSI = Serial bus master receiver (SWSD = 1 and
TRMD = 0):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
SSI = Slave transmitter/ receiver (SWSD = 0):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed. To terminate
the transfer, clear SSICR.EN to 0 and continue to
input the WS signal until SSICR.IDST becomes 1.
Note: If the external device stops the serial bus
R/W
R/W
24
0
8
0
SSI_SDATA
This bit must be set to 1 when CPEN = 1. A
one-clock cycle delay is not supported when
the SSI module is configured to be a slave
transmitter (SWSD = 0 and TRMD = 1). In this
situation, this bit should be set to 0.
R/W
R/W
use operations other than slave
transmitter (SWSD = 0 and TRMD = 1).
23
clock before the current system word is
completed then this bit will never be set.
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
0
5
R/W
R/W
20
0
4
0
REJ09B0554-0200
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0