HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 833

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits
31 to
11
10
9
8
Bit Name
⎯
RWE
RWC
IR
Initial Value
All 0
0
0
0
R/W
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. Always write 0 to
these bits.
Remote Wakeup Enable
This bit is used by HCD to enable/disable the
remote wakeup function simultaneously with the
detection of an upstream resume signal.
0: Remote wakeup function is not supported
1: Remote wakeup function is supported
This function is not supported. Always write 0 to this
bit.
Remote Wakeup Connected
This bit indicates whether or not HC supports a
remote wakeup signal. When the remote wakeup is
supported and used in the system, HC must set this
bit during POST in the system firmware. HC clears
the bit simultaneously with the hardware reset, but
not with the software reset.
0: Remote wakeup signal is not supported
1: Remote wakeup signal is supported
This function is not supported. Always write 0 to this
bit.
Interrupt Routing
This bit determines the routing of interrupts
generated by the event registered in
HcInterruptStatus. HCD clears this bit to 0
simultaneously with the hardware reset, but not with
the software reset. HCD uses this bit as a tag to
indicate the ownership of the host controller.
0: All interrupts are routed to normal bus interrupt
1: Setting prohibited
mechanism
Rev. 2.00 Feb. 12, 2010 Page 749 of 1330
REJ09B0554-0200