HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 826

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.5.2
To terminate a slave mode data transfer, after setting SSICR.EN to 0, supply the SSI_WS signal at
the active level (alternate continuous input at the high or low level for the system word length)
until SSICR.IDST becomes 1 (for five or more system words). If the SSI_WS signal is stopped
before IDST becomes 1, the SSI module will not be able to correctly terminate the transfer and
will stop in the transfer interrupted state. If SSICR.EN is set to 1 from this state, incorrect data
may be transmitted due to restarting from the interrupted state. Note that to restart the data
transfer, if the module is in the IDST = 1 state, it can be restarted from the first or second WS edge
from EN = 1.
SSI internal state
Rev. 2.00 Feb. 12, 2010 Page 742 of 1330
REJ09B0554-0200
SSISR.IDST
SSI_SDATA
SSICR.EN
SSI_WS
SCK
Notes on Stopping SSI Module Slave Mode Operation
Figure 20.25 Slave Mode SSI Transfer Termination/Restart Timing
One system word
Data transfer
Transfer termination, idle transition phase
The transfer restarts from the first or second
falling edge (when WSPS = 0) after EN = 1.
Continuously input SSI_WS until IDST = 1
(5 or more system words)
Idle/data transfer restart