HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 12

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
9.4.5 Interrupt
Exception Handling and
Priority
Table 9.7 Interrupt
Exception Handling
Sources and Priority
Order
10.5 Register
Descriptions
Table 10.6 Register
Configuration (2)
10.5.5 Wait Control
Register 1 (WCR1)
Table 10.7 Idle
Insertion between
Accesses
10.5.7 Wait Control
Register 3 (WCR3)
Rev. 2.00 Feb. 12, 2010 Page x of lxxxii
REJ09B0554-0200
Page
242
259
273
282
Revision (See Manual for Details)
Table amended
Interrupt Source
Note amended
Notes: 1. For details, refer to the descriptions of SDMR.
Note added
Notes:
2. On the MPX interface, a WCR1 idle wait may be inserted
(a) Synchronous DRAM set to RAS down mode
(b) Synchronous DRAM accessed by on-chip DMAC
Under conditions other than conditions (a) and (b) above, an
idle wait is also inserted between an MPX interface write
access and an immediately following access to the same area.
Table and note amended
Notes: n = 0 to 6; m = 1 and 4
MFI
Bit
4n + 1
4n
4m + 3 AmRDH
before an access (either read or write) to the same area
after a write access. An example of idle wait insertion in
accesses to the same area is shown below.
Bit
Name
AnH1*
AnH0*
MFII
* For area 1, only use the combinations listed in table
10.9 for the settings.
Initial
Value
All 1
All 1
All 0
INTEVT
Code
H'E80
R/W
R/W
R/W
R/W
Description
Area n Data Hold Time
For writing, specifies the number of cycles to be inserted
during the data hold time after the write strobe is
negated. For reading, specifies the number of cycles to
be inserted during the data hold time after the data
sampling timing. Valid only for SRAM interface, byte
control SRAM interface, and burst ROM interface:
00:
01:
10:
11:
Read-Strobe Negate Timing
For reading, these bits specify the timing for the negation
of read strobe. These bits should be cleared to 0 when
byte control SRAM interface is in use.
See figure 10.12.
Cycles to be inserted during the data hold time
0
1
2
3