HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1105

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.1
Table 28.1 shows the pin configuration for the H-UDI.
Table 28.1 Pin Configuration
Pin Name
Clock
Mode
Reset
Data Input
Data Output
Emulator
Input/Output Pins
Abbreviation
TCK
TMS
TRST
TDI
TDO
ASEBRK/
BRKACK
I/O
Input
Input
Input
Input
Output Data Output
Input/
Output
Function
Functions as the serial clock input pin
prescribed in the JTAG standards. Data input
to the H-UDI via the TDI pin or data output via
the TDO pin is performed in sync with this
signal.
Mode Select Input
Changing this signal in sync with a TCK signal
determines the significance of data input via
the TDI pin. Its protocol conforms to the JTAG
standards (IEEE standards 1149.1).
H-UDI Reset Input
This signal is received asynchronously with a
TCK signal. Asserting this signal low resets
the JTAG interface circuit. At power- on,
assert the TRST pin low for a given period,
whether or not JTAG is used. This differs from
the IEEE standards.
Data Input
Entering this signal in sync with a TCK signal
will send data to the H-UDI circuit.
Reading this signal in sync with a TCK signal
will read out data from the H-UDI circuit.
Emulator Connection Only
Rev. 2.00 Feb. 12, 2010 Page 1021 of 1330
REJ09B0554-0200
When Not
in Use
Open*
Open*
Connected
to ground
*
Open*
Open
Open*
2
*
3
1
1
1
1