HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 794

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.3.1
SSICR is a 32-bit readable/writable register that controls the IRQ, selects each polarity status, and
sets operating mode.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 710 of 1330
REJ09B0554-0200
Bit
31 to 29 ⎯
28
27
26
25
24
23
22
R/W:
R/W:
Bit:
Bit:
Control Register (SSICR)
Bit Name
DMEN
UIEN
OIEN
IIEN
DIEN
CHNL1
CHNL0
SCKD
R/W
31
15
R
0
-
-
SWSD
R/W
30
14
0
-
-
R
SCKP
R/W
29
13
R
0
-
-
Initial Value
⎯
0
0
0
0
0
0
0
DMEN
SWSP
R/W
R/W
28
12
0
0
SPDP
R/W
R/W
UIEN
27
11
0
0
SDTA
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OIEN
26
10
0
0
PDTA
R/W
R/W
IIEN
25
0
0
9
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
DMA Enable
Enables or disables the DMA request.
0: DMA request disabled.
1: DMA request enabled.
Underflow Interrupt Enable
0: Underflow interrupt disabled
1: Underflow interrupt enabled
Overflow Interrupt Enable
0: Overflow interrupt disabled
1: Overflow interrupt enabled
0: Idle interrupt disabled
1: Idle interrupt enabled
Data Interrupt Enable
0: Data interrupt disabled
1: Data interrupt enabled
Channels
These bits indicate the number of channels in
each system word. These bits are ignored if
CPEN = 1.
00: 1 channel per system word
01: 2 channels per system word
10: 3 channels per system word
11: 4 channels per system word
Idle Mode Interrupt Enable
DIEN
R/W
R/W
DEL
24
0
8
0
CHNL1
R/W
R/W
BREN
23
0
7
0
CHNL0
R/W
R/W
22
0
6
0
DWL2
CKDV
R/W
R/W
21
0
0
5
DWL1
R/W
R/W
20
4
0
0
MUEN
DWL0
R/W
R/W
19
3
0
0
SWL2
CPEN
R/W
R/W
18
2
0
0
SWL1
TRMD
R/W
R/W
17
1
0
0
SWL0
R/W
R/W
16
EN
0
0
0