HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1215

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
13 to 11 —
10
9 ,8
7
6
5, 4
3
Bit Name
PCBA
—
DBEB
PCBB
—
SEQ
Initial Value
All 0
—
All 0
—
—
All 0
—
R/W
R
R/W
R
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Instruction Access Break Select A
Specifies whether a channel A instruction access
cycle break is to be effected before or after the
instruction is executed.
0: Channel A PC break is effected before
1: Channel A PC break is effected after instruction
Reserved
These bits are always read as 0. The write value
should always be 0.
Data Break Enable B
Specifies whether the data bus condition is to be
included in the channel B break conditions. When
the data bus is included in the break conditions,
bits IDB1 to IDB0 in BBRB should be set to B'10 or
B'11.
0: Data bus condition is not included in channel B
1: Data bus condition is included in channel B
break conditions
PC Break Select B
Specifies whether a channel B instruction access
cycle break is to be effected before or after the
instruction is executed.
0: Channel B PC break is effected before
1: Channel B PC break is effected after instruction
Reserved
These bits are always read as 0. The write value
should always be 0.
Sequence Condition Select
Specifies whether the conditions for channels A
and B are to be independent or sequential.
0: Channel A and B comparisons are performed as
1: Channel A and B comparisons are performed as
break conditions
instruction execution
execution
instruction execution
execution
independent conditions
sequential conditions (channel A → channel B)
Rev. 2.00 Feb. 12, 2010 Page 1131 of 1330
REJ09B0554-0200