HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 238

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Tag
• V bit (validity bit)
• U bit (dirty bit)
Rev. 2.00 Feb. 12, 2010 Page 154 of 1330
REJ09B0554-0200
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 7.5,
Effective address
31
22
19
MMU
IIX
25
Entry
selection
8
255
Compare
way 0
0
Figure 7.2 Configuration of Instruction Cache
Hit signal
[12]
Address array
(way 0, way1)
19 bits
Tag
Compare
way 1
1 bit
V
3
32 bits
LW0
13 12 11 10
32 bits
LW1
Data array (way 0, way 1)
32 bits
LW2
[11:5]
32 bits
Read data
LW3
5 4
32 bits
LW4
32 bits
LW5
Longword (LW)
selection
2
32 bits
0
LW6
32 bits
LW7
LRU
1 bit