HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 942

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 858 of 1330
REJ09B0554-0200
Bit
8
7
6
5
4
3
Bit Name
FFEN
LMSB
CSV
CSA
TFIE
ROIE
Initial Value
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Enables or disables the FIFO mode. When FIFO
mode is enabled two 8-entry deep FIFOs are
made available, one for transmit data and one for
receive data. These FIFOs are read and written
via SPTBR and SPRBR. When FIFO mode is
disabled the SPTBR and SPRBR are used
directly so new data must be written to SPTBR
and read from SPRBR for each and every
transfer. FIFO mode must be disabled if DMA
requests are also going to be used to service
SPTBR and SPRBR.
0: FIFO mode disabled
1: FIFO mode enabled
LSB/MSB First Control
0: Data is transmitted and received most
1: Data is transmitted and received least
Controls the value output from the chip select
when the HSPI is a master and the chip select
generation has been selected.
0: Chip select output is low.
1: Chip select output is high.
0: Chip select output is automatically generated
1: Chip select output is manually controlled, with
0: Transmit complete interrupt disabled
1: Transmit complete interrupt enabled
Enable
0: Receive overrun occurred / warning interrupt
1: Receive overrun occurred / warning interrupt
FIFO Mode Enable
Chip Select Value
Automatic/Manual Chip Select
Transmit Complete Interrupt Enable
Receive Overrun Occurred / Warning Interrupt
significant bit (MSB) first.
significant bit (LSB) first.
during data transfer.
its value being determined by the CSV bit.
disabled
enabled