HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1088

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
27.3.3
The MFISCR is a 32-bit readable/writable register which is used to control the MFI mode and
state.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1004 of 1330
REJ09B0554-0200
Bit
31 to 8
7 to 0
Bit
31 to 7
6
R/W:
R/W:
Bit:
Bit:
MFI Status/Control Register (MFISCR)
Bit
Name
STATUS7
to
STATUS0
Bit
Name
SCRM
D2
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
Initial
Value
All 0
1
29
13
R
R
0
0
-
-
Initial
Value
All 0
All 0
28
12
R
R
0
0
-
-
R/W
R
R/W*
R/W
R
R/W
27
11
R
0
R
0
-
-
26
10
R
R
0
-
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
MFI mode 2
Specifies the MFI bus width. Changing this bit
immediately takes effect to change the bus width.
0: 8-bit mode
1: 16-bit mode
Note: In order to check for malfunctions, perform a
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
General status
These bits can be read from and written to by the
software of an MFI-connected external device and by
the on-chip CPU. These bits are not modified by
hardware other than a power-on reset.
25
R
R
-
0
9
0
-
dummy reading of MFISCR after changing this bit.
24
R
R
0
8
0
-
-
23
R
0
7
0
R
-
-
R/W*
SCR
MD2
22
R
1
0
6
-
1
21
R
R
0
0
5
-
-
SCR
MD0
20
R
0
4
0
R
-
19
R
0
3
0
R
-
-
18
R
0
2
0
R
-
-
EDN
R/W
17
R
0
1
-
0
R/W
BO
16
R
0
0
-
0

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