HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1144

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
29.7.6
(1) Condition
There is the case of stopping or NOT starting of A/D conversion in SCAN mode or MULTI mode,
because ADC can not detect the changing of ADST when the period of ADST changing is shorter
than the sampling period of the clock cycle selected with CKSL1,0.
For example, the A/D conversion may not be started depending on the setting timing of ADST,
even though ADST is set to 1(ADST = 1) to start the A/D conversion again after the A/D start bit
(ADCSR.ADST = 0) was cleared to stop conversion during the A/D operation.
(2) Workaround
It is possible to evade by the method of following (a) or (b).
(a) When ADC is used in SCAN mode, or ADC is stopped AD conversion by ADST = 0 during
Table 29.6 AD Conversion Time
Unit: cycle
(b) Leave it longer than the 1 cycle of the selected clock with CKSL1, 0 (Table 29.7) of the A/D
Table 29.7 ADST Transition Period
Rev. 2.00 Feb. 12, 2010 Page 1060 of 1330
REJ09B0554-0200
AD Conversion Time
ADST Transition Period
[sec]
AD operation (ADCSR.ADF = 0) in MULTI mode, please set ADST to 1 after an interval of
AD conversion time shown table 29.6 from the time of setting ADST = 0.
Control/Status Register (ADCSR) according to Pck in table 29.8 and the setting of the clock
dividing frequency.
Notice of Scan mode and Multi mode of A/D conversion
Pck/4
134
2'B00
4/Pck
Pck/8
266
2'B01
8/Pck
ADCSR.CKSL1, 0
Pck/16
530
2B'10
16/Pck
Pck/32
1058
2'B11
32/Pck

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