HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 936

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.1
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and
specifies the clock polarity and frequency.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 852 of 1330
REJ09B0554-0200
Bit
31 to 8
7
6
R/W:
R/W:
Bit:
Bit:
Control Register (SPCR)
Bit Name
⎯
FBS
CLKP
31
15
R
R
-
-
-
-
30
14
-
R
-
R
-
-
29
13
R
R
-
-
-
-
Initial Value
All ⎯
0
0
28
12
R
R
-
-
-
-
27
11
R
R
-
-
-
-
R/W
R
R/W
R/W
26
10
R
R
-
-
-
-
25
R
R
-
9
-
-
-
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
Controls the timing relationship between each bit
of transferred data and the serial bit clock.
0: The first bit transmitted from the HSPI module
1: The first bit transmitted from the HSPI module
0: HSPI_CLK signal is not inverted and so is low
1: HSPI_CLK signal is inverted and so is high
First Bit Start
Serial Clock Polarity
24
R
R
8
-
-
-
-
is set up such that it can be sampled by the
receiving device on the first edge of HSPI_CLK
after the HSPI_CS pin goes low. Similarly the
first received bit is sampled on the first edge of
HSPI_CLK after the HSPI_CS pin goes low.
is set up such that it can be sampled by the
receiving device on the second edge of
HSPI_CLK after the HSPI_CS pin goes low.
Similarly the first received bit is sampled on the
second edge of HSPI_CLK after the HSPI_CS
pin goes low.
when inactive.
when inactive.
R/W
FBS
23
R
7
0
-
-
CLKP
R/W
22
R
6
0
-
-
R/W
IDIV
21
R
5
0
-
-
CLKC4 CLKC3 CLKC2 CLKC1 CLKC0
R/W
20
R
4
0
-
-
R/W
19
R
3
0
-
-
R/W
18
R
2
0
-
-
R/W
17
R
1
0
-
-
R/W
16
R
0
0
-
-