HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1008

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.3.10 HAC Control Register (HACACR)
HACACR is a 32-bit read/write register used for controlling the HAC interface.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 924 of 1330
REJ09B0554-0200
Bit
31
30
29
28, 27
26
25
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
DMARX16
DMATX16
⎯
TX12_ATOMIC
⎯
31
15
R
R
-
1
0
-
RX16
DMA
R/W
30
14
-
R
0
0
TX16
DMA
R/W
29
13
R
0
0
-
28
12
R
R
0
0
Initial Value
1
0
0
All 0
1
0
-
-
27
11
R
R
0
0
-
-
ATOMIC
TX12_
R/W
26
10
R
1
-
0
R/W
R
R/W
R/W
R
R/W
R
25
R
R
-
0
9
0
-
RXDMAL
R/W
_EN
24
R
0
8
0
-
Description
Reserved
Always 1 for read and write.
16-bit RX DMA Enable
0: Disables 16-bit packed RX DMA mode.
1: Enables 16-bit packed RX DMA mode.
16-bit TX DMA Enable
0: Disables 16-bit packed TX DMA mode.
1: Enables 16-bit packed TX DMA mode.
Reserved
Always 0 for read and write.
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that
in HACCSDR separately. (Setting prohibited)
1: Transmits TX data in HACCSAR and that
in HACCSDR in the same frame if bit 19 in
HACCSAR is 0 (write). (HACCSAR must be
written last.)
Reserved
Always 0 for read and write.
TXDMAL
R/W
_EN
23
R
0
7
0
Enables the RXDMAL_EN and
RXDMAR_EN settings.
Disables the RXDMAL_EN and
RXDMAR_EN settings.
Enables the TXDMAL_EN and
TXDMAR_EN settings.
Disables the TXDMAL_EN and
TXDMAR_EN settings.
-
RXDMAR
R/W
_EN
22
R
0
0
6
-
TXDMAR
R/W
_EN
21
R
0
5
0
-
20
R
R
0
4
0
-
-
19
R
R
0
3
-
0
-
18
R
R
0
2
0
-
-
17
R
R
0
1
-
0
-
16
R
R
0
0
0
-
-