HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 316

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• INTMSK00
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 232 of 1330
REJ09B0554-0200
Bit
31 to 28
27, 26
25 to 16
15
14 to 0
R/W:
R/W:
Bit:
Bit:
Bit Name
R/W
31
15
R
1
0
R/W
R/W
30
14
1
1
R/W
R/W
29
13
1
1
Initial Value
All 1
All 0
All 1
0
All 1
R/W
R/W
28
12
1
1
R/W
27
11
R
1
0
R/W
26
10
R
1
0
R/W
R/W
R
R/W
R
R/W
R/W
R/W
25
1
9
1
Description
Interrupt Masks 31 to 28
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Masks 25 to 16
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
Reserved
This bit is always read as 0. The write value
should always be 0.
Interrupt Masks 14 to 0
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
R/W
R/W
24
1
8
1
R/W
R/W
23
1
7
1
R/W
R/W
22
1
1
6
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1