HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 302

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.5.4
With some instructions, such as instructions that make two accesses to memory, and the
indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple
exceptions occur. Care is required in these cases, as the exception priority order differs from the
normal order.
• Instructions that make two accesses to memory
• Indivisible delayed branch instruction and delay slot instruction
Rev. 2.00 Feb. 12, 2010 Page 218 of 1330
REJ09B0554-0200
With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS
instructions, two data transfers are performed by a single instruction, and an exception will be
detected for each of these data transfers. In these cases, therefore, the following order is used
to determine priority.
1. Data address error in first data transfer
2. TLB miss in first data transfer
3. TLB protection violation in first data transfer
4. Initial page write exception in first data transfer
5. Data address error in second data transfer
6. TLB miss in second data transfer
7. TLB protection violation in second data transfer
8. Initial page write exception in second data transfer
As a delayed branch instruction and its associated delay slot instruction are indivisible, they
are treated as a single instruction. Consequently, the priority order for exceptions that occur in
these instructions differs from the usual priority order. The priority order shown below is for
the case where the delay slot instruction has only one data transfer.
1. A check is performed for the interrupt type and re-execution type exceptions of priority
2. A check is performed for the interrupt type and re-execution type exceptions of priority
3. A check is performed for the completion type exception of priority level 2 in the delayed
4. A check is performed for the completion type exception of priority level 2 in the delay slot
5. A check is performed for priority level 3 in the delayed branch instruction and priority
6. A check is performed for priority level 4 in the delayed branch instruction and priority
levels 1 and 2 in the delayed branch instruction.
levels 1 and 2 in the delay slot instruction.
branch instruction.
instruction.
level 3 in the delay slot instruction. (There is no priority ranking between these two.)
level 4 in the delay slot instruction. (There is no priority ranking between these two.)
Priority Order with Multiple Exceptions