HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 232

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The following two kinds of operation can be used on UTLB data array 1:
1. UTLB data array 1 read
2. UTLB data array 1 write
6.6.6
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2 and the entry
is specified by bits [13:8].
In the data field, bit [3] indicates TC and bits [2:0] indicate SA.
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
Rev. 2.00 Feb. 12, 2010 Page 148 of 1330
REJ09B0554-0200
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
UTLB Data Array 2
Address field
Data field
SZ[1:0]:
Figure 6.16 Memory-Mapped UTLB Data Array 1
31
31
1 1 1 1 0 1 1 1 0
PPN:
D:
V:
E:
29 28
Physical page number
Validity bit
Entry
Page size bits
Dirty bit
24
23
22
PPN
PR[1:0]:
WT:
SH:
C:
:
Protection key data
Cacheability bit
Share status bit
Write-through bit
Reserved bits (write value should be 0,
and read value is undefined )
14 13
E
10 9 8 7
V
8 7
SZ1
PR[1:0]
6 5
SZ0
4 3
C
2 1 0
D
SH
WT
0