HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 562

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6.10 Switching Data for Left and Right Channels
When HAC handles the transfer of 16-bit (word) audio data, it performs the alignment such that
the left channel data is the most-significant word and the right channel data is the least-significant
word.
When SSI handles the transfer of 16-bit audio data, however, it performs the alignment such that
the left channel data is the least-significant word and the right channel data is the most-significant
word. Therefore, the difference must be taken into consideration when performing transfers
between HAC and SSI. For DMA transfer of audio data, specify
DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 10 for one channel to adjust the alignment.
11.6.11 LCDC DMA Transfer
Figure 11.38 shows a DMA transfer flow for the LCDC.
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REJ09B0554-0200
Data transferred to LCDC
Has transfer completed?
Set DMAC registers
Data stored in FIFO
Set LCDC registers
DMA transfer
Transfer end
Transfer start
Figure 11.38 Example of LCDC Data Transfer Flow
Yes
No
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Set DMAOR, DMARCR, and DMARSRA so that
DMABRG can be used.
Set LCDC registers. For details of LCDC register
settings, see section 30, LCDC Controller (LCDC).
DMA transfer is started by a DMA transfer request
output from the LCDC. Data in synchronous DRAM
is stored in FIFO of DMABRG.
The data stored in FIFO is transmitted to the LCDC.
DMA transfer is repeated until the DMA transfer
request from the LCDC is stopped.