HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 45

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6 DMABRG Operation ....................................................................................................... 467
11.7 Usage Notes ..................................................................................................................... 485
Section 12 Clock Pulse Generator (CPG).........................................................487
12.1 Features ............................................................................................................................ 487
12.2 Input/Output Pins ............................................................................................................. 490
12.3 Clock Operating Modes ................................................................................................... 491
12.4 Register Descriptions ....................................................................................................... 493
12.5 Frequency Changing Method........................................................................................... 498
12.6 Usage Notes ..................................................................................................................... 501
Section 13 Watchdog Timer (WDT).................................................................503
13.1 Features ............................................................................................................................ 503
13.2 Register Descriptions ....................................................................................................... 504
11.5.1 Examples of Transfer between External Memory and an External Device with
11.6.1 DMABRG Request ............................................................................................. 467
11.6.2 DMABRG Reset ................................................................................................. 467
11.6.3 DMA Transfer Operating Mode for HAC and SSI ............................................. 468
11.6.4 DMA Audio Receive Operation.......................................................................... 470
11.6.5 DMA Audio Transmit Operation ........................................................................ 470
11.6.6 Auto Reload Function ......................................................................................... 473
11.6.7 Forced Termination of DMA Audio Transfer..................................................... 473
11.6.8 Double Buffer Control for Audio Data ............................................................... 476
11.6.9 HAC/SSI Endian Conversion Function............................................................... 476
11.6.10 Switching Data for Left and Right Channels ...................................................... 478
11.6.11 LCDC DMA Transfer ......................................................................................... 478
11.6.12 USB DMA Transfer ............................................................................................ 479
11.6.13 USB Endian Conversion Function ...................................................................... 481
11.6.14 DMABRG Interrupts .......................................................................................... 484
12.4.1 Frequency Control Register (FRQCR)................................................................ 494
12.4.2 Clock Division Register (DCKDR) .................................................................... 496
12.4.3 Module Clock Control Register (MCKCR) ........................................................ 497
12.5.1 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 Is Off) ............ 498
12.5.2 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 Is On)............. 498
12.5.3 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 Is On) ... 499
12.5.4 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 Is Off)... 499
12.5.5 Changing Frequency Division Ratio of CPU Clock or Peripheral Clock ........... 499
12.5.6 Switching between PLL Circuit 3 On/Off........................................................... 499
12.5.7 Changing DCK Output Clock Division Ratio..................................................... 500
12.5.8 Controlling DCK Output Clock .......................................................................... 500
12.5.9 Controlling CKIO Output Clock......................................................................... 501
DACK ................................................................................................................. 465
Rev. 2.00 Feb. 12, 2010 Page xliii of lxxxii
REJ09B0554-0200