HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 582

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.5
There are two methods of changing the clock frequency: by switching off and on PLL circuit 1,
and by changing the frequency division ratio of each clock. In both cases, control is performed by
software by means of FRQCR, MCKCR, and DCKDR. These methods are described below.
12.5.1
When PLL circuit 1 is turned on, the oscillation stabilization time for PLL circuit 1 is required.
The oscillation stabilization time is counted by the on-chip WDT.
1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT.
2. Set the PLL1EN bit to 1.
3. This LSI operation stops temporarily, and the WDT starts counting up. The internal clock stops
4. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI
12.5.2
When PLL circuit 2 is on, the oscillation stabilization time for PLL circuit 1 and PLL circuit 2 is
required.
1. Make WDT settings as in step 1 in section 12.5.1.
2. Set the PLL1EN bit to 1.
3. This LSI operation stops temporarily, PLL circuit 1 starts oscillation, and the WDT starts
4. After the WDT count overflows, PLL circuit 2 starts oscillation. The WDT resumes its up-
5. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI
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The following settings are necessary:
TME bit in WTCSR = 0: WDT stopped
CKS2 to CKS0 bits in WTCSR: WDT count clock frequency division ratio
WTCNT: Initial counter value
and an unstable clock is output to the CKIO pin.
resumes operation. The WDT stops after overflowing.
counting up. The internal clock stops and an unstable clock is output to the CKIO pin.
count from the value set in step 1 above. Even during this time, the internal clock is stopped
and an unstable clock is output to the CKIO pin.
resumes operation. The WDT stops after overflowing.
Frequency Changing Method
Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 Is Off)
Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 Is On)