HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 557

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Direct Memory Access Controller (DMAC)
11.6.6
Auto Reload Function
The DMAC stops a DMA transfer for the HAC or SSI when the transfer of data bytes specified by
DMAATXTCR or DMAARXTCR is complete. When the transfer is complete, the settings
specified before the transfer are read out from DMAARXDAR or DMAATXSAR. When
restarting a transfer with the same start address and the same transfer bytes, write 1 to the DMA
activation bit (RDE or TDE bit) in DMAACR to reactivate the DMAC. It is not necessary to re-
specify the DMAARXDAR or DMAATXSAR value.
When the auto reload setting bit (RAR or TAR bit) in DMAACR is 1, the DMAC is automatically
reactivated and performs transfers between the transmit/receive buffer and audio codec repeatedly.
To terminate a DMA transfer with the auto reload enabled, write 1 to the DMA forced termination
bit (RDS or TDS bit) in DMAACR.
11.6.7
Forced Termination of DMA Audio Transfer
To forcibly terminate a DMA transfer while the transfer of data bytes specified by DMAATXTCR
or DMAARXTCR is incomplete, write 1 to the DMA termination bit (RDS or TDS bit) in
DMAACR. In a forced termination, a transfer end interrupt is also generated.
In a forced termination, the number of transfer bytes remaining on termination is indicated in
DMAATXTCNT or DMAARXTCNT. The DMA audio transfer counter loads the DMAATXTCR
or DMAARXTCR value on activation of the DMAC (when the RDE or TDE bit in DMAACR is
set to 1) and is decremented every time a DMA transfer is performed. When resuming the DMA
transfer after a forced termination, check the DMA transfer counter value for transfer progress, re-
specify the start address and number of transfer bytes, and then reactivate the DMAC.
Since DMA audio data is transferred using FIFO, all received data may not be stored in the receive
buffer at forced termination. When the DMA forced termination bit (RDS bit) in DMAACR is
read as 0, the data is completely stored.
Re-specifying the registers with the RDS or TDS bit set to 1 does not activate the DMA. Clear the
DMA enable bit of the SSI or HAC to 0 before forcibly terminating a transfer.
Figure 11.34 shows the forced termination procedure for the DMA audio transfer.
Rev. 2.00 Feb. 12, 2010 Page 473 of 1330
REJ09B0554-0200