HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 97

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

1.4
Table 1.2 lists the pin configuration of the BP-256F (21 mm*
configuration of the BP-256B (17 mm*
and input/output, respectively. In the GPIO column, O indicates a pin which also functions as a
general I/O port.
Notes: 1. HD6417760BP200AD, HD6417760BP200ADV
Table 1.2
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
2. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD,
Pin Description
Pin Name
EXTAL
XTAL
VDD-CPG
VDD-PLL1
SSI0_SCK/HAC_SD_IN0/BS2
HSPI_TX/SIM_D/MCDAT
HSPI_CLK/SIM_CLK/MCCLK
CMT_CTR1
CMT_CTR3
SCIF2_CLK
SCIF2_TXD
SCIF2_RXD
SCIF2_CTS
SCIF2_RTS
SCIF0_CLK
SCIF0_TXD
MD4/CE2B
DACK0
VDD-PLL3
UCLK
RESET
VSS-CPG
VDD-PLL2
HD6417760BL200ADV
Pin Configuration (BP-256F: 21 mm)
2
). In the I/O column, I, O, and IO indicate input, output,
I/O
O/IO/IO
I
O
⎯
⎯
IO/I/O
IO/O/O
IO
IO
IO
O
I
IO
IO
IO
O
IO
O
⎯
I
I
⎯
⎯
Function
External input clock/crystal resonator
Crystal resonator
CPG VDD
PLL1 VDD
SSI serial clock input/HAC serial data/bus start 2
HSPI transmit data/SIM data transfer/MMCIF data
HSPI serial clock/SIM clock/MMCIF clock
CMT counter
CMT counter
SCIF serial clock
SCIF transmit data
SCIF receive data
SCIF modem control
SCIF modem control
SCIF serial clock
SCIF transmit data
Mode control 4/PCMCIA-CE
DMAC0 bus acknowledge
PLL3 VDD
USB operation clock
Reset
CPG GND
PLL2 VDD
Rev. 2.00 Feb. 12, 2010 Page 13 of 1330
1
), and table 1.3 lists the pin
REJ09B0554-0200
GPIO
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
*
*
1
2