HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 40

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.7
Section 4 Instruction Set................................................................................... 67
4.1
4.2
4.3
4.4
Section 5 Pipelining.......................................................................................... 87
5.1
5.2
5.3
5.4
Section 6 Memory Management Unit (MMU)................................................. 113
6.1
6.2
6.3
6.4
6.5
Rev. 2.00 Feb. 12, 2010 Page xxxviii of lxxxii
REJ09B0554-0200
3.6.2
Usage Notes ..................................................................................................................... 63
3.7.1
3.7.2
3.7.3
3.7.4
Execution Environment.................................................................................................... 67
Addressing Modes ........................................................................................................... 69
Instruction Set .................................................................................................................. 73
Usage Note....................................................................................................................... 84
4.4.1
Pipelines........................................................................................................................... 87
Parallel-Executability....................................................................................................... 94
Execution Cycles and Pipeline Stalling ........................................................................... 97
Usage Note....................................................................................................................... 112
Overview of the MMU..................................................................................................... 113
6.1.1
Register Descriptions ....................................................................................................... 121
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
TLB Functions ................................................................................................................. 128
6.3.1
6.3.2
6.3.3
MMU Functions............................................................................................................... 134
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
MMU Exceptions............................................................................................................. 137
Pair Single-Precision Data Transfer.................................................................... 62
Rounding Mode and Underflow Flag ................................................................. 63
Setting of Overflow Flag by FIPR or FTRV Instruction .................................... 64
Sign of Operation Result when Using FIPR or FTRV Instruction...................... 65
Notes on Double-Precision FADD and FSUB Instructions ................................ 65
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction
(H'FFFD)............................................................................................................. 84
Address Spaces ................................................................................................... 115
Page Table Entry High Register (PTEH) ............................................................ 122
Page Table Entry Low Register (PTEL) ............................................................. 123
Page Table Entry Assistance Register (PTEA) ................................................... 124
Translation Table Base Register (TTB) .............................................................. 124
TLB Exception Address Register (TEA) ............................................................ 125
MMU Control Register (MMUCR) .................................................................... 125
Unified TLB (UTLB) Configuration .................................................................. 128
Instruction TLB (ITLB) Configuration............................................................... 131
Address Translation Method............................................................................... 132
MMU Hardware Management ............................................................................ 134
MMU Software Management ............................................................................. 134
MMU Instruction (LDTLB)................................................................................ 134
Hardware ITLB Miss Handling .......................................................................... 135
Avoiding Synonym Problems ............................................................................. 136