HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 518

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Dual Address Mode
Rev. 2.00 Feb. 12, 2010 Page 434 of 1330
REJ09B0554-0200
Dual address mode is used to access both the transfer source and the transfer destination by
address. The transfer source and destination can be either on-chip peripheral module or
external address.
Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source
or transfer destination.
Since in dual address mode, data corresponding to the size specified by the TS bit in CHCRn is
read from the transfer source in the data read cycle and is written to the transfer destination in
the data write cycle, it is transferred in two bus cycles. In this process, the transfer data is
temporarily stored in the data buffer in the bus state controller (BSC).
In a transfer between external memories such as that shown in figure 11.8, data is read from
external memory into the BSC’s data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 11.9 shows the timing for this operation. The DACK output
timing is the same as that of CSn in a read or write cycle specified by the AM bit in CHCRn.
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
Taking the DAR value as the address, the data stored in the BSC’s data buffer is
written to the transfer destination module.
DMAC
DMAC
BSC
BSC
Figure 11.8 Operation in Dual Address Mode
Data buffer
Data buffer
SAR
DAR
SAR
DAR
2nd bus cycle
1st bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module