HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 945

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.4
23.4.1
Figure 23.2 shows the flow of a transmit/receive operation procedure.
Depending on the settings of SPCR, the master transmits data to the slave on either the falling or
rising edge of HSPI_CLK and samples data from the slave on the opposite edge. The data transfer
between the master and slave completes when the transmit complete status flag (TXFN) in SPSR
is set to 1. This flag should be used to identify when an HSPI transfer event (byte transmitted and
byte received) has occurred, even in the case where the HSPI module is being used to receive data
only (null data being transmitted). By default data is transmitted MSB first, but LSB first is also
possible depending on how the LMSB bit in SPSCR is set.
During the transmit function the slave responds by sending data to the master synchronized with
the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the
shift register in the module and on completion of the transmit function, is transferred to SPRBR.
Operation
Operation Overview without DMA (FIFO Mode Disabled)
Yes
mode by setting the MASL bit
setting TFIE and ROIE bits in
Select required interrupts by
Select master or slave
Write data to SPTBR
TXBUFF is empty by
reading the TXFL bit
transmit required?
Reset the system
Figure 23.2 Operational Flowchart
in SPSCR
in SPSR
Check if
Another
SPSCR
Start
End
No
Yes
No
Rev. 2.00 Feb. 12, 2010 Page 861 of 1330
HSPI_TX data to/from slave
REJ09B0554-0200