HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 17

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
17.3 Register
Descriptions
Table 17.2 Register
Configuration (1)
17.3.14 Serial Error
Register (SCRER)
17.6 Usage Notes
(7) Notes on the TEND
Flag
19.3.1 Slave Control
Register (ICSCR)
Page
574
575
601
626
667
Revision (See Manual for Details)
Table amended
Ch. Register Name
0
1
Ch. Register Name
2
Figure and table amended
Initial value:
Description added
Table amended
Bit
2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transmit FIFO data count
register 0
Receive FIFO data count
register 0
Transmit FIFO data count
register 1
Receive FIFO data count
register 1
Transmit FIFO data count
register 2
Receive FIFO data count
register 2
R/W:
Bit:
Bit Name
SIE
Bit Name
PER6
PER5
PER4
PER3
PER2
PER1
PER0
FER6
FER5
FER4
FER3
FER2
FER1
FER0
15
—
—
R
0
-
PER6 PER5 PER4 PER3 PER2 PER1 PER0
14
R
0
13
R
0
Initial Value
0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
R
0
11
0
R
Abbrev.
SCTFDR0 R
SCRFDR0 R
SCTFDR1 R
SCRFDR1 R
Abbrev.
SCTFDR2 R
SCRFDR2 R
10
R/W
R/W
R
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 2.00 Feb. 12, 2010 Page xv of lxxxii
R
R/W
R/W
9
0
Slave Interface Enable
Ensure to set this bit to 1 to have the slave to
operate. If this bit is low, the slave interface is
reset.
Description
Description
Reserved
This bit is always read as 0. The write value
should always be 0.
Number of Parity Errors
These bits indicate the number of data bytes in
which a parity error occurred in the receive data
stored in SCFRDR.
After the ER bit in SCFSR is set, the value
indicated by bits PER6 to PER0 is the number of
data bytes in which a parity error occurred.
If all 128 bytes of receive data in SCFRDR have
parity errors, the value indicated by bits PER6 to
PER0 will be 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
Number of Framing Errors
These bits indicate the number of data bytes in
which a framing error occurred in the receive data
stored in SCFRDR.
After the ER bit in SCFSR is set, the value
indicated by bits FER6 to FER0 is the number of
data bytes in which a framing error occurred.
If all 128 bytes of receive data in SCFRDR have
framing errors, the value indicated by bits FER6 to
FER0 will be 0.
R
8
0
P4 Address
H'FE60 001C
H'FE60 0020
H'FE61 001C
H'FE61 0020
P4 Address
H'FE62 001C
H'FE62 0020
R
7
-
0
FER6 FER5 FER4 FER3 FER2 FER1 FER0
R
6
0
5
0
R
Area 7 Address Size
H'1E60 001C
H'1E60 0020
H'1E61 001C
H'1E61 0020
Area 7 Address Size
H'1E62 001C
H'1E62 0020
4
0
R
REJ09B0554-0200
R
3
0
R
2
0
16
16
16
16
16
16
1
0
R
Pck
Pck
Pck
Pck
Sync
Clock
Sync
Clock
Pck
Pck
R
0
0