HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 283

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(5) Data TLB Multiple-Hit Exception
• Source: Multiple UTLB address matches
• Transition address: H'A000 0000
• Transition operations:
TLB_multi_hit()
{
}
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits
(IMASK3 to IMASK0) are set to B'1111.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections.
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
EXPEVT = H'0000 0140;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.IMASK = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;
Rev. 2.00 Feb. 12, 2010 Page 199 of 1330
REJ09B0554-0200