HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 51

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.4 Memory............................................................................................................................ 782
21.5 Data Storage Format for USB Host Controller ................................................................ 783
21.6 Restrictions on HcRhDescriptorA.................................................................................... 784
Section 22 Controller Area Network 2 (HCAN2) ............................................785
22.1 Features ............................................................................................................................ 785
22.2 Architecture...................................................................................................................... 785
22.3 Input/Output Pins ............................................................................................................. 788
22.4 Programming model – overview ...................................................................................... 789
22.5 HCAN2 Control Registers ............................................................................................... 798
22.6 Operation.......................................................................................................................... 840
21.3.17 Periodic Start Register (HcPeriodicStart) ........................................................... 766
21.3.18 Low Speed Threshold Register (HcLSThreshold) .............................................. 767
21.3.19 Root Hub Descriptor A Register (HcRhDescriptorA) ........................................ 768
21.3.20 Root Hub Descriptor B Register (HcRhDescriptorB) ......................................... 770
21.3.21 Root Hub Status Register (HcRhStatus) ............................................................. 772
21.3.22 Root Hub Port Status 1 Register (HcRhPortStatus1) .......................................... 774
21.5.1 Storage Format of Transfer Data......................................................................... 783
21.5.2 Storage Format of the Descriptor........................................................................ 784
22.2.1 Block diagram..................................................................................................... 785
22.2.2 Block Function.................................................................................................... 787
22.4.1 Memory map....................................................................................................... 789
22.4.2 Mail box.............................................................................................................. 790
22.5.1 Master Control Register (CANMCR) ................................................................. 806
22.5.2 General Status Register (CANGSR) ................................................................... 812
22.5.3 Bit Configuration Registers 1 and 0 (CANBCR1, CANBCR0).......................... 813
22.5.4 Interrupt Request Register (CANIRR)................................................................ 818
22.5.5 Interrupt Mask Register (CANIMR) ................................................................... 823
22.5.6 Transmit Error Counter and Receive Error Counter (CANTECREC) ................ 824
22.5.7 Transmit Pending Request Registers 1 and 0 (CANTXPR1, CANTXPR0) ....... 825
22.5.8 Transmit Cancel Registers 1 and 0 (CANTXCR1, CANTXCR0) ...................... 827
22.5.9 Transmit Acknowledge Registers 0 and 1 (CANTXACK1, CANTXACK0) ..... 829
22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0).......... 830
22.5.11 Receive Data Frame Pending Registers 1 and 0
22.5.12 Remote Frame Request Pending Registers 1 and 0
22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0) .... 834
22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0).......... 835
22.5.15 Timer Counter Register (CANTCNTR).............................................................. 836
22.5.16 Timer Control Register (CANTCR).................................................................... 837
22.5.17 Timer Compare Match Registers (CANTCMR) ................................................. 839
(CANRXPR1, CANRXPR0) .............................................................................. 832
(CANRFPR1, CANRFPR0)................................................................................ 833
Rev. 2.00 Feb. 12, 2010 Page xlix of lxxxii
REJ09B0554-0200