HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1154

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
12
11
10
9
8
7, 6
Rev. 2.00 Feb. 12, 2010 Page 1070 of 1330
REJ09B0554-0200
Bit Name
DPOL
⎯
MCNT
CL1CNT
CL2CNT
⎯
Initial Value R/W
0
0
0
0
1
All 0
R/W
R
R/W
R/W
R/W
R
Description
Display Data Polarity Select
Selects the polarity of the LCD_DATA (display data)
for the LCD module. This bit supports reflection of
the LCD module.
0: LCD_DATA is high active, transparent-type LCD
1: LCD_DATA is low active, reflective-type LCD
Reserved
This bit is always read as 0. The write value should
always be 0.
M Signal Control
Sets whether or not to output the LCD's current-
alternating signal of the LCD module.
0: M (AC line modulation) signal is output
1: M signal is not output
CL1 (Horizontal Sync Signal) Control
Sets whether or not to enable LCD_CL1 output
during the vertical retrace period.
0: LCD_CL1 is output during vertical retrace period
1: LCD_CL1 is not output during vertical retrace
LCD_CL2 (Dot Clock of LCD Module) Control
Sets whether or not to enable CL2 output during the
vertical retrace period.
0: LCD_CL2 is output during vertical retrace period
1: LCD_CL2 is not output during vertical retrace
Reserved
These bits are always read as 0. The write value
should always be 0.
panel
panel
period
period