HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1147

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the palette memory to determine the colors, then puts the display on the LCD panel. It is possible
to connect the LCDC to the LCD module of most types other than microcomputer bus interface
types and NTSC/PAL types and those that apply the LVDS interface.
30.1
The LCDC has the following features.
• Panel interface
• Supports 4/8/15/16-bpp (bits per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024*
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
• Dedicated display memory is unnecessary using part of the SDRAM connected to area 3 of the
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel's signal polarity
• Supports the selection of data formats (the endian setting for bytes, backed pixel method) by
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit
⎯ Serial interface method
⎯ Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width) *
control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker.
CPU as system memory.
register settings
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels—see table 30.4).
2. For details, see section 30.4.1, Size of LCD Modules Which Can Be Displayed with
Features
lines should be connected to GND or to the lowest bit from which data is output.
this LCDC.
Section 30 LCD Controller (LCDC)
Rev. 2.00 Feb. 12, 2010 Page 1063 of 1330
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