HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 420

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

CPU
DMAC dual
DMAC single
Table 10.17 Availability of Pipelined Access for Cycles
Previous Access
O: Pipelined access available
X: Pipelined access not available
(9) Refreshing
The bus state controller is provided with a function for controlling refreshing of the synchronous
DRAM. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH
bit to 1 in MCR. If synchronous DRAM is not accessed for a long period of time, both the
RMODE bit and the RFSH bit can be set to 1 to activate self-refresh mode, which uses low power
consumption for data retention.
(a) Auto-Refreshing
Rev. 2.00 Feb. 12, 2010 Page 336 of 1330
REJ09B0554-0200
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to
CKS0 in RTCSR and the value set in RTCOR. Bits CKS2 to CKS0 and RTCOR should be set
to satisfy the refresh interval specification for the synchronous DRAM that is used. First make
the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, and then make the
CKS2 to CKS0 setting last. When the clock is selected by CKS2 to CKS0, RTCNT starts
counting up from the value at that time. The RTCNT value is constantly compared with the
RTCOR value, and if the two values are the same, a refresh request is generated and an auto-
refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted.
Figure 10.27 shows the auto-refresh operation and figure 10.29 shows the synchronous DRAM
auto-refresh timing.
First, an REF command is issued in the TRr2 cycle. A new command is not output for the
duration of (TRr cycles) + (number of cycles specified by bits TRAS2 to TRAS0 in MCR) +
(number of cycles specified by bits TRC2 to TRC0 in MCR). Bits TRAS2 to TRAS0 and
TRC2 to TRC0 must be set to satisfy the synchronous DRAM refresh cycle time specification
(active−active command delay time).
Read
Write
Read
Write
Read
Write
X
X
X
O
O
O
Read
CPU
X
X
X
O
O
O
Write
O
O
X
O
O
O
Read
Next Access
DMAC Dual
X
X
X
X
X
X
Write
O
O
X
O
O
O
Read
DMAC Single
O
O
X
O
O
O
Write