HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 734

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
(4) Smart card mode register (SISCMR) settings
When the IC card is set for the direct convention, both the SDIR and SINV bits are set to 0; for the
inverse convention, both are set to 1. The SMIF bit is always set to 1.
Figure 18.3 shows the register settings and initial character waveform examples for two types of
IC cards (a direct-convention type and an inverse-convention type).
For the direct-convention type, the logical level 1 is assigned to the Z state, and the logical level 0
to the A state, and transmission and reception are performed LSB-first. The data of the above
initial character is then H'3B. Even parity is used according to the smart card specification, and so
the parity bit is 1.
For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical level
0 to the Z state, and transmission and reception are performed MSB-first. The data of the above
initial character is then H'3F.
Even parity is used according to the smart card specification, and so the parity bit is 0, assigned to
the Z state.
Inversion by the SINV bit setting only applies to data bits D7 to D0. To invert the parity bit,
specify odd parity through the SISMR.O/E bit, both for transmission and reception.
Rev. 2.00 Feb. 12, 2010 Page 650 of 1330
REJ09B0554-0200
(Z)
Figure 18.3 Examples of Initial Character Waveforms
(Z)
(b) Inverse convention (SDIR = SINV=O/E = 1)
(a) Direct convention (SDIR = SINV=O/E = 0)
Ds
Ds
A
A
D7
D0 D1
Z
Z
D6
Z
Z
D5
D2
A
A
D4
D3
Z
A
D3
D4
Z
A
D2
D5
Z
A
D1
D6
A
A
D0
D7
A
A
Dp
Dp
Z
Z
(Z)
(Z)
state
state

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