HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 72

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 LCD Controller (LCDC)
Figure 30.1 LCDC Block Diagram.......................................................................................... 1064
Figure 30.2 Valid Display and the Retrace Period .................................................................. 1092
Figure 30.3 Color-Palette Data Format.................................................................................... 1094
Figure 30.4 Power-Supply Control Sequence and States of the LCD Module ........................ 1099
Figure 30.5 Power-Supply Control Sequence and States of the LCD Module ........................ 1099
Figure 30.6 Power-Supply Control Sequence and States of the LCD Module ........................ 1100
Figure 30.7 Power-Supply Control Sequence and States of the LCD Module ........................ 1100
Figure 30.8 Clock and LCD Data Signal Example.................................................................. 1106
Figure 30.9 Clock and LCD Data Signal Example.................................................................. 1106
Figure 30.10 Clock and LCD Data Signal Example.................................................................. 1107
Figure 30.11 Clock and LCD Data Signal Example.................................................................. 1107
Figure 30.12 Clock and LCD Data Signal Example.................................................................. 1108
Figure 30.13 Clock and LCD Data Signal Example.................................................................. 1109
Figure 30.14 Clock and LCD Data Signal Example.................................................................. 1109
Figure 30.15 Clock and LCD Data Signal Example.................................................................. 1110
Figure 30.16 Clock and LCD Data Signal Example.................................................................. 1110
Figure 30.17 Clock and LCD Data Signal Example.................................................................. 1111
Figure 30.18 Clock and LCD Data Signal Example.................................................................. 1112
Figure 30.19 Clock and LCD Data Signal Example.................................................................. 1113
Figure 30.20 Clock and LCD Data Signal Example.................................................................. 1114
Figure 30.21 Clock and LCD Data Signal Example.................................................................. 1115
Figure 30.22 Clock and LCD Data Signal Example.................................................................. 1116
Section 31 User Break Controller (UBC)
Figure 31.1 Block Diagram of UBC........................................................................................ 1120
Figure 31.2 User Break Debug Support Function Flowchart .................................................. 1140
Section 33 Electrical Characteristics
Figure 33.1 EXTAL Clock Input Timing ................................................................................ 1230
Figure 33.2 CKIO Clock Output Timing (1) ........................................................................... 1231
Figure 33.3 CKIO Clock Output Timing (2) ........................................................................... 1231
Figure 33.4 DCK Clock Output Timing (1) ............................................................................ 1231
Figure 33.5 DCK Clock Output Timing (2) ............................................................................ 1232
Figure 33.6 Power-On Oscillation Settling Time (1)............................................................... 1232
Figure 33.7 Standby Return Oscillation Settling Time
Figure 33.8 Power-On Oscillation Settling Time (2)............................................................... 1233
Figure 33.9 Standby Return Oscillation Settling Time
Figure 33.10 Standby Return Oscillation Settling Time (Return by NMI)................................ 1234
Figure 33.11 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0) ................. 1234
Rev. 2.00 Feb. 12, 2010 Page lxx of lxxxii
REJ09B0554-0200
(Return by RESET or MRESET) (1).................................................................... 1233
(Return by RESET or MRESET) (2).................................................................... 1234